Existing multipliers which operate on pairs of binary operands suffer from several deficiencies which contribute to the prolongation of their multiplication operations. For example, the addition of the partial products requires the propagation of carry bits which can require an extensive increment in time necessary for the carry bits to fully propagate through all of the binary bit orders. A second problem is that the addition of the partial products is conventionally done in a sequential manner in order to avoid undue complexity in the adder circuitry. Parallel operations, which could otherwise shorten the duration of the addition of the partial products, cannot be conveniently carried out without complex arithmetic circuitry capable of handling multiple carry bits generated in any particular bit column.